Verification Engineer - UVM

HR Central
  • Bangalore
  • Confidential
  • 3-8 years
  • 31 Jul 2015

  • Project/ Program Management IT

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

3 to 8 years of experience in Verification with BSEE/MSEE.
Very good System Verilog/UVM/OVM knowledge with prior work experience on live projects.
Expertise in creating detailed test plan with well-defined functional coverage goals.
Should be able to architect and implement self - generating / self- checking simulation verification environment to reach functional coverage goals using random/directed stimulus.
Knowledge of scripting language like Perl, Shell, TCL or Python.
Very Good debugging skills.
Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams .
Experience in running and debugging Gate level simulations.
Successful experience in 802.11 Wireless VLSI designs or other related technologies is a big plus.
Knowledge of protocols like AXI and ARM subsystems and top level interconnects is plus.
Highly motivated and independent contributor with good aptitude and attitude.

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