- Engineer would be responsible for doing physical design implementation, timing closure and Physical verification at block level. He/She would be communicating to client directly.
- He/She should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
- Expert in Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation.
- Good understanding on low power concepts
- Good understanding on top level physical design, partitioning and timing constraints, IR Drop.
- Expert in static timing analysis/fixing, power and noise analysis
- Good understanding in Physical Verification
- Knowledge in automation script (Tcl, Perl, etc) would be an added advantage.
- Good communication skills is a MUST.
- Experience leading small teams (3-5) is a plus (Primarily for Tech Lead)
Years of experience: 5 plus years .