Job Overview / Description
Responsible for the overall verification of digital logic blocks for mixed signal data communications product from architectural specification. The role encompasses developing testbenches, testplans and testcases for block level, IP level and SoC level.
o Capture and analysis of design requirements
o Creation of functional verification plan based on requirements
o Identification of suitable IP blocks and creates specifications for BFM/Stub development.
o IC architecture development (block architecture, interfaces, etc.)
Developing a robust verification plan and environment with different methodologies
o Specification to model testbench
o Architecting layered, Class based automated testbenches
o Hands-on development experience with Constrained Random test-bench using High Level Verification Languages(SystemVerilog/VERA preferred)
o Deploying SystemVerilog assertions (SVA) or OpenVera assertions (OVA)
o Developing and integrating verification IP
o Experience in verification environment development using OVM/VMM/UVM
o Emulation / silicon validation experience is plus
o Strong knowledge on Perl, UNIX shell, or equivalent scripting languages
o Generating and Analyzing Code Coverage reports.
o PCIE or DDR or USB or SATA or Networking protocols work experience
o DSP experience is a plus
Hands-on experience with multiple ASIC tapeouts (or Spec to Release cycle) is a plus
Must have excellent English written and verbal communication and interpersonal skills.
Experience in leading and mentoring teams is a plus
Experience and Qualification
BTech/BE or MTech (preferred) in Electrical Engineering
Overall experience between 6 to 9 years will be required a minimum of 5+ years of verification experience is must.