Lead - High Speed PHY/IO Design
We Have opening with Semiconductor Product Base Company in Bangalore location. If your interested with below Job description please send your update resume to pranava,tpATgsconsultingDOTin
Experience: 6 - 12 years
Education: Bachelors or Master's (preferred) Degree in Engineering
Required PHY Experience:
- Circuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies (65nm - 10nm) in one or more of the following:
- One or more High speed Serdes Interfaces (1Gbps-30Gbps. PCIe, MIPI, HDMI, USB, SATA, XFI, HMC, HDM, 10GKR etc.)
- High speed Memory interfaces (DDR3/4, LPDDR3/4, GDDR)
Required analog sub-block experience:
- Circuit design experience in two or more of the following sub-blocks in deep sub-micron technologies (65nm-10nm):
- PLL, DLL, Clock data recovery and low skew clock delivery
- High speed receiver and transmitter front end and calibration methods
- High speed I/O cell designs: LVTTL/LVCMOS, LVDS, HSTL, SSTL
- Analog sub-blocks like high speed amplifiers, high speed comparators, voltage regulators and high performance latches.
- At least one production silicon
- Post-silicon debug and bring-up exposure
- Analog layout exposure (self-layout or work with mask designer)
- Ability to work & communicate with cross functional teams, overseas teams, and strong oral & written communication skills.
- Experience with industry standard tools such as Spectre, Hspice, AMS verification, EM/IR flows & tools (Apache, Voltus), MATLAB, Calibre/StarRC, Apache, Voltus
- Understanding of Mismatch analysis & MonteCarlo methodology/sims, transistor level & Circuit level noise analysis. Understanding of device physics & deep-sub micron issues
- Thorough understanding of PDK and complex rules for deep-sub micron nodes including DRC, LVS extraction, analog matching and latchup rules.
- Working knowledge of UNIX/LINUX environments, shells and scripting.
- Exposure to ESD protection
- You will be part of a highly skilled high speed PHY design team working on challenging high speed PHY in latest foundry nodes (28nm, 14nm and below). Most of the work will be in DDR3/4 and LPDDR3/4 designs.
- You will undertake high speed analog/mixed signal designs of significant complexity and should be able to deliver high quality designs efficiently
- For senior people, you will need to take ownership of complex analog sub-blocks inside the PHY and drive the specification, schedule and implementation including transistor and block level design, simulation, reliability, mixed mode simulations etc. You may need to technically supervise junior engineers.
- Drive layout of complex blocks through mask designers. Conform to complex process rules as well as DFM.
- Participate in design reviews both internally and potentially with customers to explain design choices and robustness. Work with people across multiple sites including overseas.
- Help with creatingIP views: Behavioral/Verilog-A, timing views, abstract etc.
- Participate in silicon bring up, characterization, & perform Si correlations against models & simulations