Fully responsible for signoff PD, and layout signoff flow in physical design team.
Experience implementing complex IP/ASIC Physical Design, experience with SoC floorplan/padring/placement/cts experience.
Technical hands-on capability
Desired experience using Synopsys ICC with good TCL scripting skills
Timing : should be able to drive the timing closure, constraints definition/cleanup. Desired experience using Synopsys PT