Experience in backend flow including physical design, timing analysis to final tape out in 28nm and below. Hands on experience in standard backend tool flows is a must.
Strong back ground of ASIC physical design: Floor planning, P&R, extraction, IR D
Provide technical guidance, mentoring to Physical Design Engineers Interface with front-end ASIC teams to resolve issues
Low Power Design - Voltage islands, power gating, substrate-bias techniques. Timing closure on DDR2/DDR3/PCIE interfaces