Develop & implement DFT - BIST flows , generate ATPG vectors, simulate. Be hands-on & lead junior engineers. 5+ yrs of exp in DFT. Deep understanding of SA / TFT / BIST technologies for digital / analog designs
Familiar with LBIST/scan compressor architecture. Very familiar with test vector generation & simulation. Familiar with yield enhancement / DPPM reduction techniques. 5+ yrs of exp in DFT.
Si debug & correlation exp is plus. In-test experience