Chip Lead - Physical Design

Allegro Solutions
  • Ahmedabad
  • 10-15 lakh
  • 9-13 years
  • 17 Sep 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Key Qualifications:
The ideal candidate will have 9+ years of physical design experience, with recent successful tapeouts in deep submicron technologies(45nm and below).Strong knowledge of PD construction & analysis flows and methodology. Knowledge of all aspects of ASIC physical design process, from RTL design to ASIC bring up.

- Proven ability to manage a large PD design team.

- Proven ability to execute to stringent schedule & die size requirements. Strong communication skills. Able to understand the requirements of other functional teams, and ability to navigate and negotiate win-win solutions for the project.

- Lead physical design team with following responsibilities,.

- Work independently and with multisite teams in the areas of RTL to GDSII implementation.

- Well versed with Synthesis, Die size estimation, partitioning, IO Planning, constraints validation, Full Chip Floor planning, Metal Layer estimation-planning, timing budget generation, power planning, IR/EM Drop Flows, Full Chip Signoff STA, Block Level Signoff STA, Place and Route, and Physical Verification DRC/LVS/ERC, DFM.

- Interface with full chip timing, block build, hard-macro, packaging, architecture, foundry, design automation and design technology teams to resolve various issues in timely manner. Participate in project planning, scheduling and reviews- Help in org development, hiring, identify skill gaps and team building activities.

- You will also be responsible for driving methodology development, automation, collaborate with other design teams, share best practices followed.

- Experienced in industry standard tools used and their capabilities & underlying algorithms ( Synopsys ICC or SoC Encounter OR Mentor Olympus )

- Sound expertise in Tcl, Perl, Shell scripting

- Needs to work from customer site in the US during requirements of Project kick off, mid reviews and hand over.

Technical Skill [Required]:

(1) Synopsys ICC, PT-PTSI, DC, OR EDS/SoCEncounter

(2) Taking care of full chip SOC PD issues (including IO ring design, Hierarchical design planning,.Timing sign off, PnR, Power sign off, Mentor Calibre based LVS-DRC Closure and Sign off).

(3) Working at Geometry at 65, 45, 28nm and below.

Soft Skills [Required]:

(1) This job involves working from customer site.

(2) Highly motivated technical person who wants to grow experience building large ASIC and exposure to work with multi-site team.

Qualification: BE/B.Tech/ME/M.Tech

Competencies/Skill sets for this job

Timing Sign Off PnR Power Sign Off Synopsys ICC PT-PTSI DC

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About Organisation

Allegro Solutions