A_physical Design, STA, Soc,ip Timing Closure,high Speed Complex Desig

Talent HR Solutions
  • Ahmedabad, Bangalore
  • 15-30 lakh
  • 5-10 years
  • 01 Sep 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Experience on SOC and/or IP Timing closure and signoff of high speed complex design with multiple clocks and power domains, Experience in setting up timing constraints, analyzing STA timing reports, driving timing closure at the block and chip level

Competencies/Skill sets for this job

Sta Design SOC Physical Design Timing Constraints

Job Posted By

About Organisation

Talent HR Solutions