A_verification Ip(vip) R&D Engineer-exp in Pcie,usb3,100gigabit Ethern

Talent HR Solutions
  • Ahmedabad, Bangalore
  • 10-20 lakh
  • 5-10 years
  • 272 Views
  • 01 Sep 2015
dfdf

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Candidate must have experience in developing VIP (verification IPs / IPs verification) such as PCIe, USB3, 100 Gigabit Ethernet and AMBA bus protocols for use with RTL simulation,EDA(Electronic design Automation) Domain with VIP development.
Bus Protocol know how with SV, OVM, UVM, VMM, Specman. knowhow etc,Experience with System Verilog or System C. Knowledge of assertion languages such as SVA, PSL.
Solid Verilog HDL RTL knowledge, Asic verification , SOC Verification , VLSI verification


Competencies/Skill sets for this job

Verification Specman Rtl Simulation Ethernet Verilog Eda Uvm Pcie

Job Posted By

About Organisation

Talent HR Solutions