Technical Lead / Sr. Engineer [Functional Verification (Digital)] at Japan location.
- Someone who is motivated technical person with business development skills at multi-site environment and have an ability to speak, read & write Japanese language fluently is the need of organization.
- The person will be responsible to work at Japan location and act as a representative with clients.
- Need to have Minimum 5+ years experience in SV and UVM / OVM / VMM based ASIC / FPGA verification with coverage driven verification skills.
- He should be well versed with architecting test benches and should have done at least 2 SOC verification projects in SV/ UVM.
- Should have experience in leading module level verification independently performing RTL and gate level verifications of SoC and design IPs.
- B.E., B.TECH, M.E. M. TECH (Bachelor or Master Degree)
- Expertise in System Verilog, Verilog and C/C++.