Design Methodology / Integration Engineers

Brainsearch Consulting
  • Bangalore, Delhi, Hyderabad
  • 10-15 lakh
  • 5-10 years
  • 03 Apr 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Develop & execute physical aware synthesis, timing closure at synthesis & perform equivalence checks. Do RTL bottleneck analysis , refine RTL & do synthesis closure for high-speed designs. Experience in design integration & synthesis
Has done RTL integration , synthesis, verification (LEC/Formality), timing analysis. Familiar with topo/graphical /physical synthesis flows. Can refine RTL or flow for speed improvement. Exposure to Physical design is plus. Masters in education

Competencies/Skill sets for this job

Synthesis Rtl Timing Closure Verification Closure Design Methodology

Job Posted By

Mandeep M
Account Manager

About Organisation

Brainsearch Consulting