Synthesis / STA Engineer

Brainsearch Consulting
  • Bangalore, Delhi, Hyderabad
  • 10-15 lakh
  • 3-8 years
  • 23 Jun 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Minimum 3 yrs working exp with top/block level timing closure (STA), timing closure methodologies. Good exp in EDA tools : PrimeTime, Deep Sub Micron topics, clock tree designs & CCD. Well versed with tcl / Perl script.
Synthesis & Timing closure on 28nm / 20nm / 16nm technologies based designs. Co-work with RTL engineers & DFT engineers to consolidate modem subsystem timing constraints along with toplevel SOC requirements . Verify timing constraints with CCD

Competencies/Skill sets for this job

Perl Sta Ccd Perl Script Rtl Soc

Job Posted By

Mandeep M
Account Manager

About Organisation

Brainsearch Consulting