A Engineer should handle Independently Full Chip / SOC planning and execution from Netlist-to-GDSII.
Hands on Expertise to all aspects of design flows like floorplanning, placement, CTS, routing, crosstalk avoidance and physical verification.
Very good understanding and hands on experience with the timing closure (STA), timing closure methodologies, ECO generation.
Very good hands on Experience on physical verification (DRC/LVS/ERC/Ant). Well versed with parasitic extraction.
Must have worked on the up to 40nm Physical Design.
Should be able to provide clear directions to the team wrt PNR issues.
Drive methodology with help of local and external CAD/EDA teams for fasterdesign convergence.
Well aware of place and route methodologies and hands on experience with Low power methodologies.
Experience in leading block level or full chip level Timing closure & Physical Design activities.
Work independently in the areas of RTL netlist to GDSII implementation.
Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)
Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
Tcl/Perl scripting knowledge is essential.
Willing to handle technical deliveries with a small team of engineers.
Expertise in Synopsys ICC, STA (PrimeTime, SI), StarRC-XT, Mentor Calibre for DRC/LVS/ERC/Ant and Redhawk for Dynamic and Static IR drop.
9-15 yrs experience in Physical Design Execution.
Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 9+ years of experience in Physical Design.
Good team player.
Good communication skill to negotiate with top level for convergence.
Strong problem-solving skills and teamwork, Self-motivated, excellent verbal and written communication.