Staff Engineer/ Senior Design Engineer

INFINITY HR Consulting Pvt Ltd
  • Bangalore
  • Confidential
  • 6-9 years
  • 132 Views
  • 30 Jul 2015
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  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

Requirements:

* BS / MS in EE/CSE from a reputed University.

* Strong understanding of DFT methodologies and tooling.

* Experience on SoCs with multiple scan chains and clocks.

* SCAN chain implementation at chip and block level.

* MBIST implementation at chip and block level.

* JTAG implementation at chip and block level.

* Gate simulation setup and debug.

* Test mode timing constraint development and analysis is a plus.

* Understanding of test compression and ATE debug is a plus.

* DFT architecture experience is a plus.

* Self-driven individual and an excellent team player experienced in working with remote teams.

* Must have good communication skills and the ability and desire to work as a team.



Job Description:

The selected candidate will be a lead contributor who is responsible for:

* SCAN, MBIST and JTAG implementation, verification, vector generation and ATE post-silicon debug for complex 40nm and 28nm processor products.

* Contribute to JTAG implementation and verification.

* Contribute to MBIST implementation and verification.

* Contribute to overall DFT methodology/tooling for 28nm flow.

* Contribute to SoC DFT SCAN, MBIST and JTAG architecture.

* Contribute to SCAN, MBIST and JTAG timing constraints/analysis.



Responsibilities:

* Responsible for SCAN insertion, scan DRC analysis and debug.

* Responsible for achieving high SCAN coverage and low DPPM.

* Responsible for SCAN, MBIST and JTAG gate-level simulations.

* Responsible for ATPG vector generation and ATE debug.


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INFINITY HR Consulting Pvt Ltd