STA / Synthesis Experts

Roland & Associates
  • Bangalore
  • 10-20 lakh
  • 7-10 years
  • 90 Views
  • 31 Dec 2015
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  • Project/ Program Management IT

  • IT/ Technology - Software/ Services
Job Description

BS or MS degree in EE or related with 3+ years working experience with top/block level timing closure (STA), timing closure methodologies.

Ability to understand clock tree designs

Co-work with RTL engineer and DFT engineer to consolidate modem subsystem timing constraints.

Verify timing constraints with CCD.

Analyze pre-layout and post-layout timing, develop timing ECOs, and work closely with layout engineers to achieve full chip timing closure.

Good experience in EDA tools : PrimeTime, and CCD


Competencies/Skill sets for this job

Timing Closure Sta Synthesis Ccd Rtl Dft Eda

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About Organisation

Roland & Associates