STA / Synthesis Experts

Roland & Associates
  • Bangalore
  • Confidential
  • 3-10 years
  • 105 Views
  • 31 Dec 2015
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  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Experience : 3 - 10 Years

Location : Bangalore

  • BS or MS degree in EE or related with 3+ years working experience with top/block level timing closure (STA), timing closure methodologies.
  • Ability to understand clock tree designs
  • Co-work with RTL engineer and DFT engineer to consolidate modem subsystem timing constraints.
  • Verify timing constraints with CCD.
  • Analyze pre-layout and post-layout timing, develop timing ECOs, and work closely with layout engineers to achieve full chip timing closure.
  • Good experience in EDA tools : PrimeTime, and CCD
Mail your Resume to pd@roljobs.com
 


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