Background in the synthesis and timing closure of large digital designs with multiple clock domains.
Development in timing constraints for multiple clock domain and derived clocks.
Implementation and synthesis of digital designs for low power implementation.
Scan insertion and Memory Bist insertion experience.
Low power design techniques a plus.
Working with place and route team on translation of the constraints and timing closure activities.
Static timing closure experience for tapeout signoff.
7+ years of experience in digital implementation for sub-micron processes.
BE/M.Tech in Electronics Engineering.
Emphasis in digital circuit design would be a plus.