Skill Set: ASIC Physical Design
At least 4 years of experience in the following skills - Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process technology
Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formailty, and Caliber.
At least 4 years of experience in Project life cycle activities on development and maintenance projects.
At least 4 years of experience in Physical Design and STA review.
At least 4 years of experience in ASIC development life cycle.
Ability to work in team in diverse/ multiple stakeholder environment