Job Profile :
Good knowledge of Hierarchical scan synthesis with :
o Scan segmentation's
o Test models
Handle module level scan insertion.
Handle device scan insertion with multiple clock domains.
Able to do Block/ Device level pattern generation and simulations.
Scan interleaved with memory bist patterns gen and validation.
Device level transition delay testing with multiple clocks, handling exceptions.
Able to do Sequential ATPG with RAMs and latches, coverage analysis.
Path Delay tests, delay coverage analysis.
Excellent knowledge on usage of ATPG tool.-
Able to do Silicon debug and diagnostics
Delay tests using PLL, silicon debug and diagnostics.
Good knowledge of On-chip scans compression or bist techniques and test time reduction.
Memory BIST integration in SoC and verification, selecting the optimal mem.