Physical Design Lead

Allegro Solutions
  • Bangalore, Delhi
  • 10-20 lakh
  • 10-15 years
  • 12 Mar 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

A)Full Chip PD Lead:

Detailed Description of the Job Profile:

In this highly visible role, you will be the lead responsible for the physical implementation (from netlist to tapeout) of a highly complex SOC utilizing state of the art process technology.

Key Qualifications:

The ideal candidate will have 10+ years of physical design experience, with recent successful tape outs in deep submicron technologies (28nm and below).Strong knowledge of PD construction & analysis flows and methodology. Knowledge of all aspects of ASIC physical design process, from RTL design to ASIC bring up.

- Proven ability to manage a large PD design team.

- Proven ability to execute to stringent schedule & die size requirements. Strong communication skills. Able to understand the requirements of other functional teams, and ability to navigate and negotiate win-win solutions for the project.

- Lead physical design team with following responsibilities,.

- Work independently and with multi site teams in the areas of RTL to GDSII implementation.

- Well versed with Synthesis, Die size estimation, partitioning, IO Planning, constraints validation, Full Chip Floor planning, Metal Layer estimation-planning, timing budget generation, power planning, IR/EM Drop Flows, Full Chip Signoff STA, Block Level Signoff STA, Place and Route, and Physical Verification DRC/LVS/ERC, DFM.

- Interface with full chip timing, block build, hard-macro, packaging, architecture, foundry, design automation and design technology teams to resolve various issues in timely manner. Participate in project planning, scheduling and reviews- Help in org development, hiring, identify skill gaps and team building activities.

- You will also be responsible for driving methodology development, automation, collaborate with other design teams, share best practices followed.

- Experienced in industry standard tools used and their capabilities & underlying algorithms ( Synopsys ICC or SoC Encounter OR Mentor Olympus )

- Sound expertise in Tcl, Perl, Shell scripting

- Needs to work from customer site in the US during requirements of Project kick off, mid reviews and hand over.

(B) Top Level STA Lead:

- 10+ Yrs of experience in doing hands on Full chip STA

- STA Flow determination, Constraint completeness qualification, Constraint validation,Timing budgeting for blocks, Determine the number of modes and corners STA needs to be done.

- Determine pre-layout and post-layout STA strategy. Needed Scripting and flow automation

(C ) CAD Development Lead:

- 10+ Yrs of experience in Physical design and flow development

- Should have done flow development for the PnR activities and supported the CAD related issues in the past.

- Should have involved in multiple tapeout support in sub micron technologies

- Should have good knowledge of industry standard PnR tools

- Sound expertise in Tcl, Perl, Shell scripting

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Allegro Solutions