Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm & 65nm)
Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout.
Clear understanding and command over all aspects of physical design
Expertise in Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter
Skill and experience in scripting using Tcl or Perl desirable.