Standard Cell Characterization - Layout Engineer

Allegro Solutions
  • Bangalore
  • 10-15 lakh
  • 3-8 years
  • 12 Mar 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Candidates will be evaluated based on Primary skill set and Secondary skill set.

- 3 core competencies recognized: Characterization, Layout and scripting (Perl, TCL Python, SKILL).

- Candidate must be capable of at-least two competencies.

- Candidate who are Characterization experts (and EDA) with scripting or layout as secondary skill.

- Candidate who is layout expert with characterization or scripting skill.

SKILL set expectation:

- Ability to characterize & Model NLDM, ECSM & ECSM-N models using CDNS liberate tool

- Modelling of other EDA views like OA, LEF, Verilog, V/S, CeltIC, redHawk, ATPG

- Introduction to Voltus & Tempus & cell-aware ATPG

- Automation capability in python, SKILL (perl, TCL is also welcome)

- Duration: starting 1st Jan- 2015 till Dec- 2015

Work involved:

- Technologies: 140nm, 90nm, 65nm and 40nm

- Special cells along with basic LOGIC cells

- NLDM, ECSM, ECSM-N and CCS-N development

- Verilog, LEF generation and validation

Competencies/Skill sets for this job

Tcl Perl Scripting Python Atpg Verilog

Job Posted By

About Organisation

Allegro Solutions