Memory Layout Engineer

Allegro Solutions
  • Bangalore
  • 10-15 lakh
  • 2-5 years
  • 12 Mar 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

- Candidate must have experience in layout design of memory leaf cells and at top level of memories should have worked on 65nm / 45nm / 28nm process technologies and Good understanding of issues like WPE, LOD effects.

- He/She must have good understanding of physical verification checks. DRC, LVS, ERC and reliability checks . IR and EM.

Competencies/Skill sets for this job

Memory Layout Drc Reliability Layout Design Lod Verification

Job Posted By

About Organisation

Allegro Solutions