System DV group of market and technology leader enabling the convergence of networking, storage and clustering traffic over 40Gb Ethernet, is looking for highly skill verification engineers to verify the ASIC.
- Develop block and system-level test benches and verification environments; achieve complete coverage to ensure first working silicon.
- Adding functional coverage for the environment.
BE/ME/MCA/MSC/ BS or MS degree in Electrical Engineering, Computer Engineering or related discipline.
EXPERIENCE: - Strong programming experience using system Verilog with UVM/VMM/OVM methodology
- Networking protocol knowledge, PCIE/DDR3/MAC experience is a plus.
- Experience on PLI/VPI is a plus. - They will be responsible to develop test environment and tests to verify various Networking protocols on sub-system and system level environments.
- Develop detailed test plans and execute the testplan.