JD in detail:
1) BTech/MTech EE. IIT, BITS, IISc, preferred or equivalent experience.
2) Hands on experience in UVM / SV at least for 4 years. Experience in uVM System verilog based verification
3) High-energy individual with strong commitment, good team player, and comfortable in a fast-paced environment.
4) The person will be part of the VLSI design team, doing verification for DSL chips
5) He will be responsible for defining test bench architecture of blocks and creating test plans.
6) He will be responsible for verifying the block, creating direct and constrained random testcases.
7) He will be responsible for functional and code coverage of his blocks.
Plus: Good attitude / work hard / take initiative on own and not expect hand holding too much and be very professional.
Real Professionals are people who:
a) Need minimal supervision.
b) Can self -- declare their task completion with no checks.