To Perform highly optimized Auto Place & Route(APR), chip level layout integration and chip level verification of PIC Microcontrollers.
Floor planning and Place and Route at block level and chip level
Custom Clock Tree / Clock Tree Synthesis (CTS) methodology development
Integration of Custom and Digital blocks
Active participation in STA by identifying and executing timing ECOs
Execute tape out sign off checks (LVS, DRC, EMIR, DFM, Signal-EM)
Interact with the CAD team to ensure coordination on layout related tools/libraries/scripts for cost-effective and timely release
Interface with Design Engrs to provide feedback and implement enhancements to ensure design correctness and robustness.
B.E/B.Tech or MS in Electronics or Electrical Engineering Expert user of Synopsys ICC Floor-Planning, Place & Route and Clock Tree Synthesis Good verbal/written communication skills with local and remote teams Experience in Microcontrollers or related physical designs on 65/40nm and below Strong debugging skills including STA, CTS and Physical verification Good experience RC Extraction, Signal Integrity, IR drop analysis and Crosstalk analysis Good at scripting in TCL, PERL etc.