Senior Engineer/ Technical Lead (Verification) - US

  • US-Other
  • Confidential
  • 6-10 years
  • 06 Feb 2015

  • Project/ Program Management IT

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Job description

- Work involves executing ASIC/FPGA verification project in the role of Project Leader / Senior Engineer

- He/She should have hands on experience, client communication / interactions, in-depth technical reviews & mentoring

- Candidate should have close tracking of technical as well as management aspects.

- Having H1 visa

Desired Skills and Experience:

Hands on experience in Verification IPs design and development.

* Fluent in SystemVerilog and Verilog.

* Multiple Verification methodology knowledge, either in AVM, OVM and UVM or VMM (Synopsys), is preferred.

* Simulation tools experience with ModelSim, Questa, VCS and NC Sim.

* Strong Memory protocol knowledge (DDR2/3/4, NAND flash -- at least one).

* Experience in design, development and validation of Memory VIPs.

* Project Planning - Design, Verification and Validation Plan and Project Schedule participation.

* Architecture definition  Generic VIP architecture supporting multi language, multi tools and multi methodologies.

* Development: Memory model coding, controller coding, test sequence coding, Assertion, protocol checkers and functional coverage coding.

* Standards : JEDEC-79-2F or above, ONFI 3.0 or above.

* Team handling experience: size 5 minimum, duration 1 year minimum (TL)


6 to 10 Years

Soft Skill:-

* Attitude and Aggressive(go getter).

* Leadership abilities.

* Flexibility.