Requirement specification, functional specification, implementation specification creation
Micro-architecture of design
RTL implementation and Lint
Synthesis, static timing analysis and power analysis
Experience or knowledge of protocols like AMBA(AXI, AHB), OCP, DRAM(DDR, LP-DDR, Wide-IO), SD (UHS-I and UHS-II), eMMC, MIPI (UFS, UniPro, LLI), PCIe, USB, Ethernet protocols
Experience in VHDL / Verilog and architecture.
Experience in IP designs (Any IPs).
Experience in ASIC and SOC.
Experience in RTL frond end designing.
Experience in Memory Controller / Memory Interface (Ex: NAND flash Controller, DDR, DRAM, SDRAM, UFS, UniPro, MIPI etc...).
Experience in designing the IPs from the scratch.
Experience designing of ECC (Error Correction Code) block and knowledge of ECC
Experience on ASIC Synthesis flow and static timing flows, Formal checking, etc.
Experience of scripting (Tcl, Perl).
Knowledge of IP design project development life cycles