Research and develop EDA tool for performance analysis and optimization of external memory (DDR) bus system
Lead a team of EDA tool design engineers to develop a performance analysis framework for memory bus system
Work closely with Japan design team to get requirements and then defining plans to development
Plan, allocate resources, assign tasks and direct activities of the team to meet aggressive schedules and achieve milestone criteria
Report project status to Manager and Japan design team
Requirement specification, user guide creation
EDA tool design
EDA tool testing and evaluation
Hands on industry experience in External memory bus system performance analysis and optimization
Experience in leading a team is must.
Experience of performance modeling (System C etc)
Experience of programming (C, C++)
Experience of scripting (Tcl, Perl)
Experience of IPXACT tool development is mandatory.
Experience in VHDL is a plus.
Knowledge in verification language (Specman, System Verilog) and methodology (eRM, OVM, UVM) is a plus.
Knowledge of system bus (AMBA, OCP, NoC) and DRAM memory (DDR, LP-DDR, HBM, HMC, Wide-IO2 etc) is plus.
Knowledge of SoC domain
Knowledge of IP design project development life cycles