Roles / Responsibility :
* Individual will be responsible for performing Physical Design activities for POWER & System Z microprocessors and subsystems.
* Responsibilities includes Block-level timing closure of high frequency designs (4GHz+) such as Processor Core, Cache Controllers, interfaces like PCIe and IBM proprietary bus architectures. Includes design planning, synthesis, placement & route and critical sign-off checks to achieve required Quality of Result.
Skills and experience :
* PhD/Master's/ Bachelor's Degree in Engineering
* Skills : Physical design of server processor. You should have proven skill in floor planning, synthesis, Placement & Routing, physical design verification and other sign-off checks, timing analysis and closure. Server physical design and statistical timing experience will be a plus.
* Demonstrated communication skills (written and oral)
Experience :3 - 10Years.
* Bachelor's Degree
* At least 5 years experience in Physical Design of Server Processor
* At least 5 years experience in Synthesis, Placement, Route, floorplaning, timing analysis, PDV cleanup
* English: Fluent
* Master's Degree in Engineering