To lead a team of PD engineers to successfully tapeout multiple chips/SoCs at different process nodes for different product groups in Semtech.
Responsible for independent planning and execution of RTL-to-GDSII of SOC and full chip design.
Hands on experience in leading top level of PD of chips including IO, Bump Maps, Power grid. Experience on full-chip, Timing closure & Physical Design activities.
Based on experience, this position may be considered for a leadership role in the company.
Experience and Qualification:
BE/BTech or MTech (preferred) in Electrical Engineering.
10 + years of design experience required.
Work independently and with multisite teams in the areas of RTL to GDSII implementation.
Well versed with Synthesis, constraints validation, Full Chip Floor planning, partitioning, timing budget generation, power planning, IR/EM Drop Flows, Full Chip Signoff STA, Block Level Signoff STA, Place and Route, and Physical Verification DRC/LVS/ERC, DFM.
Proficient in Synopsys ICC or Cadence Encounter.
Would be involved in setting up the flows, automation and scripting with Perl or TCL.
RTL design experience is a plus
Working knowledge of Lynx flow from Synopsys is a plus
Experience with various process nodes (TSMC 28-65, IBM, Tower/Jazz) is a plus
Experience with multiple chip tapeouts through full Physical Design flow is a must