Candidate must have relevant experience from a good company
Candidate must have worked/led multiple full chip integration and design closure activities.
Lead SoC integration and coordinate the design closure activities
Work and interface with the customer leads to meet design goals
Work with STA leads for chip timing closure.
Work with DfT leads for meeting test closure targets.
Work with the Physical design team for design closure
Work with IP teams to meet the SoC technical and delivery requirements.
Actively contributes to methodology and flow set-up, setting design targets (timing, power, test) and work on improvements
Contribute to gate-level simulations and debug.
Technically lead/mentor team members.
Contribute in audits/reviews and work with team and design manager to achieve timely and high quality deliverables.