Principal Engineer - Physical Design

  • Mumbai, Navi Mumbai
  • Confidential
  • 13-15 years
  • 30 Apr 2015

  • Project/ Program Management IT

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor, IT/ Technology - Embedded
Job Description

Expert in Synthesis to Tapeout flow, including Layout, DFT, Timing Closure, and Chip Finishing
Ability to independently handle complex blocks to closure right from Synthesis
Worked on at least 3 end to end projects those spanned across entire life cycle of development
Ability to communicate with RTL design, and other remote teams
Excellent verbal and written communication skills Expertise on 40, 45, and 28 nm technologies
Expertise on either Cadence or Synopsys flow
Minimum 13 years of relevant experience
Leads the top level partition and timing closure of the entire chip
Works on multiple highly complex blocks taking the RTL delivery from the design team
Take the block through all phases of backend activities, including Synthesis
DFT insertion, Clock placement, Layout, Timing Closure
Physical verification Constantly interacts with design teams to provide feedback on quality of the design, feasibility, and other aspects such as power and area optimizations
Own and execute a part of state of the art, multimillion, multipower island, very large area chip in 40, 45, and 28 nm technologies
Works with other team members to help and guide the junior member in the team
As well as takes help from domain experts within the team as needed.

Competencies/Skill sets for this job

Timing Closure Physical Verification Physical Design Dft Rtl

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