Principal Engineer - Physical Design

  • Pune
  • 10-15 lakh
  • 12-15 years
  • 21 Jul 2015

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

Leads the top level partition and timing closure of the entire chip
Works on multiple highly complex blocks taking the RTL delivery from the design team, and take the block through all phases of back-end activities, including Synthesis, DFT insertion, Clock placement, Layout, Timing Closure, and Physical verification
Constantly interacts with design teams to provide feedback on quality of the design, feasibility, and other aspects such as power and area optimizations
Own and execute a part of state of the art, multi-million, multi-power-island, very large area chip in 40, 45, and 28 nm technologies
Works with other team members to help and guide the junior member in the team, as well as takes help from domain experts within the team as needed

Competencies/Skill sets for this job

Physical Design Timing Closure Verification Rtl Dft Synthesis

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