Physical Design Engineer

Cambio Consulting India Pvt Ltd
  • Hyderabad
  • Confidential
  • 3-8 years
  • 151 Views
  • 15 Jun 2015
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  • Project/ Program Management IT

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Job Description:

o 3-16 Years of experience in SoC development in Physical Design flows for state-of-the art and highly complex SoCs from Netlist to GDS, preferably in product based semiconductor companies
o Hands-on technical leadership experience with deep sub-micron technology ASIC design, STA and physical implementation; Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and Full Chip Physical Designs
o High level of expertise in complete physical implementation tool chain, Synopsys tool familiarity preferred (DC, ICC, PT, PTSI, PTPx, Star-RC) and Mentor Caliber, Tetramax and simulators
o Experience in full-chip and block-level timing constraints development, STA, timing closure and physical design, STA aspects like timing de-rates, design timing margins, Multi-Mode, Multi-Corner MMMC, and STA timing corners
o Expertise in Physical Verification and Tapeout Quality checks; Experience in Foundry and Packaging process, Packaging know-how, experience in Giga-bit interfaces, Mix-Signal IP Design attributes (PLL, SERDES, USB, PCIe) highly desirable
o Familiarity with Front-End Design, DFT Concepts, Scan, LEC
o Prior experience of mentoring team of engineers, problem solving and technical supervision


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