Looking for Physical Design engineers to execute the P&R of IPs and complex subsystems.
The engineer will be responsible for owning tapeouts of Blocks & integrates implementation environment components utilizing advanced flows and latest P&R tools.
Experience implementing complex IP/ASIC Physical Design, Preferably 4+ years experience with SoC floorplan/padring/placement/cts experience.
Strong related P&R experience;
Block level implementation & top level integration experience.
Gate design experience.