STA Physical Design Engineer

  • Bangalore
  • 10-15 lakh
  • 6-8 years
  • 24 Jun 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Full chip timing constraints development, full chip Static Timing Analysis and Signoff for a complex, multi-clock, multi-voltage SoC.- Working with Systems and Application team to drive timing closure friendly SoC architecture and IO interfaces/IO pin.- Streamlining the timing signoff criterions, timing analysis methodologies and flows (critical path spice simulation etc.) and develop/enhance auto ECO generation scripts for timing closure.- Analyze and Incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow- Enhance existing entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip level and block level.- Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level).- Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of existing processes and recommend and implement the process improvements to ensure Zero Defect chips.- Active participation in post silicon validation, correlation and test activities using in-house test and validation lab.- Encouraging and influencing technological innovations in the team.- Actively work as part of team both locally & also with remote or multi-site teams.

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