Lead ASIC Design Engineer- STA

Gobrah Management Consulting Services Pvt.
  • Bangalore
  • Confidential
  • 7-10 years
  • 19 Oct 2015

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

Should have worked on full chip synthesis using Synopsys DC / Cadence RC compiler
Experience with Synopsys PrimeTime
Must Understanding of Verilog/VHDL RTL constructs, Exposure to DDR2/3, high speed I/O timing Interface or similar a plus point
Should have flair of managing a team of 15-20 engineers & a good team player. 

Competencies/Skill sets for this job

Verilog Cadence RC Compiler Asic Design

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