Layout Engineer for WSG design group in Bangalore. This candidate will work on SOCs and individual macros for a 32-bit microcontroller product line that includes WiFi and Bluetooth capabilities.
Job responsibilities are:
Macro-level layout and sign off checks (LVS, DRC, EMIR, DFM, Signal- integrity)
Layout parasitic extraction.
Interface with Design Engineers to provide feedback and implement enhancements to ensure design correctness and robustness.
IPGEN processing of macro collateral of completed designs needed for back-end views to be used by the APR team
The candidate must have B.E. (Electronics) degree. M.E. / M. Tech (Electronics/Microelectronics) preferred.
Experience in Custom Layout and Integration is must.
The candidate must have at least 7 years of relevant experience.
Experience in analog circuits or related physical designs are preferred. Good experience in RC Extraction and Signal Integrity is required.
In depth knowledge of the Cadence suite of layout tools is a must.
The candidates ability to use constraints driven layout techniques is highly desirable.
The candidate will be working as a part of the global Wireless Solutions product development team. Strong communication skills and the ability to interface effectively with US and Taiwan team members are essential