Exp on full chip synthesis using Synopsys DC / Cadence RC compiler.
Synopsys Prime Time is Must
Understanding of Verilog/ VHDL RTL constructs
Exposure to DDR2/3, high speed I/O timing Interface or similar is plus
Strong exp on full chip synthesis using Synopsys DC / Cadence RC compiler is must
Should have flair of managing a team of 15-20 engineers & a good team player.
Excellent communication skills
B.Tech/Master's degree in electronics