Must have experience in RTL Coding.
Good in ASIC/FPGA design flows
Good experience in complex RTL IP/sub-system development
Good in FPGA based prototyping of complex SoCs/sub-systems
Hands on with programming languages Verilog, Vhdl, C, C++ and and scripting perl,TCL
Strong knowledge in low power methodologies and power aware RTL Implementation Must be having strong CommunicationResponsibilities for this position would involve:
Creating emulation/Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools.
Defining and documenting RTL changes required for emulation/FPGA. Developing hardware and software collaterals and integrating them with the emulation/FPGA model.
Testing and debugging the emulation/FPGA model and collaterals.
Defining and developing new capabilities & HW/SW tools to enable acceleration of RTL and improving emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation. Developing improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.
RTL Design coding Verification Micro architecture FPGA Synthesis implementation Verilog HDL System Verilog HP s DTL Modelsim Finsim Questasim Verilog-XL NC Vantage VCS VMC Scripting Language