SOC DV engineer with 5+ years of experience in complex design verification using C & ASM based approach.
Roles and responsibilities :
* Create digital verification plans using datasheets, inputs from engineers, and working closely with system and design engineers.
* Implement digital test-benches in Verilog (or UVM or System verilog) to apply stimulus and checks.
* Implement System Verilog Assertions (SVA) to check digital DUT behavior.
* Knowledge of formal verification based methodology.
* Knowledge of Coverage analysis for closure of verification.
* Power aware verification knowledge.
* Experience in C & ASM based verification at RTL and GLS level.
Minimum Years of Exp: 5YYRS
Minimum Education Level: B.TECH in Electrical Engineering/Electronics