Exp req is 4 to 12 years of experience in DFT Engineering
* Expert knowledge of DFT architecture on complex SoCs with multiple power and clock domains.
* Experience with standard JTAG protocol and Boundary scan.
* Experience in ATPG flows -- pattern generation, simulation and bring-up.
* Expert knowledge on Coverage improvement and Test time reduction.
* Exposure to Logic synthesis, Logic Equivalence, Scan insertion methodologies and Test Timing closure.
* Experience in DFT related RTL integration.
* Experience in industry standard DFT tools - Mentor Tessent suite, Synopsys DFT compiler.
* Experience in Low-Power DFT requirements.
* Experience in DFT related RTL integration and exposure to verification of DFx features at RTL/Gate level.
* Experience in functional vector generation for coverage improvements and for Characterization is a plus.
* Experience in Gate and RTL simulations for functional pattern generation using C/Assembly infrastructure is a plus