Senior Physical Design Engineer

  • Pune
  • 10-15 lakh
  • 5-10 years
  • 24 Jun 2015

  • IT/ Information Technology

  • IT/ Technology - VLSI/ ASIC/ EDA/ Semiconductor
Job Description

Participate in all the different phases of Physical design implementation of SoCs.- Participate in Block level Physical design of complex Chip/IPs.- Participate in STA and Timing Closure activities- Work with chip integration team closely in Timing closure- Complete the Block level / SoC Design including the Physical Design Verification- Participate in Chip Level Floor Planning and hierarchical design

- Required skills- Hands-on experience with back-end tools (Floor planing and Place & Route) preferably using ICC / Astro- Clock tree synthesis- Back-end design flows from Synthesis to Physical design verification including various Scan and BIST methodologies- Static Timing Analysis and Timing closure- Physical design verification (LVS, DRC)- Power analysis- Chip finishing flow- As part of Design Implementation team, you will be responsible for all aspects of physical design implementation from Netlist to GDSII. Applicant will also be involved in chip floor planing, power analysis, full chip integration, timing closure, and physical verification (DRC / LVS / ERC / Antenna), tapeout and mask review.- Applicant will also participate in establishing and defining implementation methodologies and flow automation. Experience should be focused on design implementation.- Doctorate - Doctorate Not Required- Requirements/Qualifications (Education) : MS EE or equivalent with 5-10 Years- Pre Requisites: BE/Masters from reputed Tier 1 education institute

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