Sr. ASIC HW Design Engineer 5-7 years of RTL design with multiple tape-outs.
Experience of multi-million gate ASIC design and verification methodologies.
Knowledge of Computer architecture Knowledge of digital design methodologies and tool flow Excellent logic design, debugging and problem solving skills Experience in logic design with Verilog and/or System Verilog and validation/verification
Experience in synthesis and timing analysis
Experience in GPU design a plus Experience with DSP, datapath design and floating point math a plus
Experience in 3D graphics pipeline and algorithms a plus
Experience in H.264 encoding decoding a plus
Knowledge of SIMD, MIMD, VLIW, and parallel processing a plus.