This person will be responsible for design and implementation of a module from start to finish for our Tegra chips. Specific areas include data path backbone design, control backbone buses. You will be expected to make architectural tradeoffs based on feature, performance requirements and system limitations, come up with micro-architecture, implement in RTL, fully verify modules through appropriate test cases and meet timing. You will also be required to support silicon validation.
- BS or MS in electrical engineering or computer engineering.
- 3+ years experience working on ASIC development.
- Knowledgeable in verilog RTL coding, synopsys design compiler, perl.
- Good communication skills and ability & desire to work as a team player are a must