This job opening provides unique opportunity to work on product from Concept to Silicon. Candidate is expected to work with senior most architect and very well experienced and vibrant team of designer/verification and implementation engineers engaged in development of state of the art storage product. This is individual contributor position.
- Hands on Contribution through designing/enhancing multi-million gate IPs from Spec to Gates. - Interact with the Chip Architect, RTL design team, IP vendors, Design Implementation team and Product Engineering team. - Provide technical leadership to a team of engineers. - Multi-Million gate SoC/ASSP integration.
Requirements: Must have: - Strong Design Background with proven IP/Chip level design contribution. - Proven capability of handling Multi-Million gate IP design/Micro-Architecture (Spec to Gates). - Proven experience of RTL Coding (Verilog), Synthesis, timing closure. - Direct technical contribution in at least 2-3 chips with exposure to full chip cycle(60nm/40nm). - Should have complete understanding of at least one high speed serial protocol like PCIe/SAS/Ethernet/Fiber channel/Infiniband etc. - Experience in design and integration of Multi-core CPU subsystem. - Experience in SoC integration. - Capability to understand Marketing Product requirement, Architecture spec. - Strong debugging and communication skills - Self starter with leadership quality, ability to positively influence/mentor juniors. Good to have - Experience with silicon bring up in lab. - Functional Verification experience with any VM/SystemVerilog, OOP concepts - Unix/Linux/Solaris exposure - ARM knowledge, AMBA bussing. - Test plan development - People Management experience. - Experience in DFT, Floor Planning, formal verification. Experience and Qualification: - 8 to 12 years - B.E/M.E/B.Tech/M.Tech in Electronics/VLSI.