Lead SoC integration and coordinate the design closure activities
* Work and interface with the customer leads to meet design goals
Work with STA leads for chip timing closure.
* Work with DfT leads for meeting test closure targets.
Work with the Physical design team for design closure
* Work with IP teams to meet the SoC technical and delivery requirements.
* Actively contributes to methodology and flow set-up, setting design targets (timing, power, test) and work on improvements
* Contribute to gate-level simulations and debug.
* Technically lead/mentor team members.
* Contribute in audits/reviews and work with team and design manager to achieve timely and high quality deliverables
Required knowledge and skills:
VLSI Design flows
Logic and Circuit design
Expertise in Verilog
* Worked on UPF/CPF based formal verification
* Worked on equivalence checks, Spyglass and constraint audit tools
Synthesis and PT- SI timing analysis for complex blocks and working through timing ECO fixes
* Worked on RTL and gate-level simulations and debug.
Worked with multi clock, rail and high speed designs.
* Worked with multi-power domain designs and experience with low power methodologies and flows.
* Worked with physical design team for timing closure.
Very good communication skills
* Outstanding analytical and critical thinking skills.
Worked on complex data path designs and/ IPs
Knowledge of power analysis tools
Expertise in scripting languages
* Knowledge with timing analysis with multi voltage designs
* Worked with hierarchical flows
* Working knowledge of Physical design tools to aid timing closure