* Proficiency in one or more HVL's a must (System Verilog,Specman, C++, Vera, e, System C, test builder).
* Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA
* Should have worked on SOC verification on at least one project with constrained random methodology (eRM/VMM/OVM).
* Must be expert in building a verification env with any of the above methodology, writing and debugging test cases.
* Good in concepts Code coverage and functional coverage.
* Expertise in Verilog and / or VHDL is desired
* Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc
* Experience in leading and managing teams
* Good communication skills
Tools: System Verilog, Verilog, Specman